This application is related to Japanese application No. HEI 11-216108 filed on Jul. 30, 1999, whose priority is claimed under 35 USC xc2xa7119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a substrate for a resin-encapsulated semiconductor device, a resin-encapsulated semiconductor device and a process for fabricating the same. More particularly, it relates to a substrate used for a resin-encapsulated semiconductor device of a ball grid array (BGA) type which is called a chip size package (CSP), and a process for fabricating the same.
2. Related Art
Conventionally, resin-encapsulated semiconductor devices of the BGA type called CSP as shown in FIG. 14(c) have been widely utilized.
The resin-encapsulated semiconductor device comprises a wiring substrate 25 for mounting a semiconductor chip which includes thereon a patterned wiring 26, a plurality of first through holes 31 for external connection and a plurality of lands 27 for external connection which cover the entire openings of the first through holes 31 and partially constitute the patterned wiring 26, and a semiconductor chip 21 mounted thereon. The semiconductor chip 21 is electrically connected to the patterned wiring 26 through wire bonding using an Au wire 23. The semiconductor chip 21 and the Au wire 23 are encapsulated with a resin 22 for encapsulation. Further, external terminals 24 for external connection are mounted on a surface opposite to a chip-mounting surface of the wiring substrate 25 and electrically connected to the semiconductor chip 21 via the lands 27.
The resin-encapsulated semiconductor device is fabricated by the following process.
First, as shown in FIGS. 9(a) and 9(b), the first through holes 31 for mounting the external terminals are formed in an area array matrix of the wiring substrate 25. On a surface of the wiring substrate 25 where the semiconductor chips 21 are to be mounted, the patterned wiring 26 and the lands 27 for external connection are formed of a conductive film, and marks 30 representative of cutting lines are formed of the conductive film in the periphery of the wiring substrate 25. The lands 27 partially serve as the patterned wiring 26 and cover the respective first through holes 31.
Then, as shown in FIGS. 10(a) and 10(b), the semiconductor chips 21 are mounted on the wiring substrate 25 and electrically connected to the patterned wiring 26 formed on the wiring substrate 25 through wire bonding using Au wires 23.
Subsequently, as shown in FIGS. 11(a) and 11(b), the semiconductor chips 21 arranged on the wiring substrate 25 and the Au wires 23 are all encapsulated in one-piece with the resin 22 by a transfer mold technique.
Then, as shown in FIGS. 12(a), 12(b), 14(a) and 14(b), the thus encapsulated semiconductor chips 21 are divided into individual chips. At this time, as shown in FIG. 14(a), a surface of the wiring substrate 25 where the external terminals are to be mounted is adhered to a jig 33 for fixing the wiring substrate. The chip-mounting surface of the wiring substrate 25 is faced upward so that the marks 30 of cutting lines can be observed from the chip-mounting surface side of the wiring substrate 25. The cutting line is defined by joining a pair of marks 30 formed on the opposite sides of the periphery of the wiring substrate 25. The resin 22 and the underlying wiring substrate 25 are cut and divided with a single cutting blade 29 along the cutting line in one operation as shown in FIG. 14(b).
Thereafter, as shown in FIGS. 13(a), 13(b) and 14(c), the external terminals 24 are mounted at the first through holes 31 from the external terminal mounting surface and subjected to a reflow process to metallically bond the external terminals 24 and the patterned wiring 26 or the lands 27. Thus, an end product is obtained.
However, in the above-described process, since the wiring substrate 25 encapsulated with the resin 22 is cut and divided into individual products by recognizing the marks 30 indicative of cutting lines provided on the wiring substrate 25 at the circumference of the resin 22, the process for mounting the external terminals 24 is performed after the division of the products. Therefore, the external terminals 24 have to be mounted on the divided resin-encapsulated semiconductor device, respectively, which decreases productivity.
Further, the marks 30 indicative of cutting lines are formed separately from the formation of the first through holes 31 so that the marks and the first through holes tends to be mal-aligned, which makes difficult to control the positional relationship between the edge of the resin 22 and the first through holes 31 after cutting.
In addition, where all the semiconductor chips 21 mounted on the wiring substrate 25 are encapsulated in one-piece with the resin 22, warpage occurs due to the difference in line expansion coefficient among the wiring substrate 25, the resin 22 and the semiconductor chips 21. Further, the greater the contact area of the wiring substrate 25 and the resin 22 is, the greater the warpage of the substrate 25 occurs.
Thus, because of the increase in warpage of the wiring substrate 25, there are problems of difficulties in conveying the wiring substrate 25 or in connecting the external terminals 24 and the lands 27 in the following fabricating process.
Moreover, in the above-described fabrication process, the semiconductor chips 21 encapsulated with the resin 22 on the wiring substrate 25 are divided into individual chips 21 by cutting. That is, the wiring substrate 25 and the resin 22 formed of different materials are cut in one operation with one cutting blade 29. Therefore, the cutting blade 29 is extremely worn out.
Further, since cut faces of the resin 22 and the wiring substrate 25 are in the same plane, the resin 22 and the wiring substrate 25 may be easily separated from each other at an interface therebetween.
The present invention provides with a substrate for resin-encapsulated semiconductor device comprising a first region for mounting semiconductor chips where a plurality of wiring patterns, a plurality of first through holes for external connection and lands which cover the entire openings of the first through holes and partially constitute the patterned wirings are formed and a second region where the semiconductor chips are not mounted, the first and second regions being formed on the same surface, wherein a plurality of second through holes whose openings are entirely covered with a conductive film are formed in the second region.
Further, the present invention provides with a process for fabricating a resin-encapsulated semiconductor device comprising the steps of: (a) forming a plurality of first through holes for external connection in a first region for mounting a semiconductor chips of a substrate for mounting the semiconductor chips and a plurality of second through holes in a second region where the semiconductor chips are not mounted; (b) forming a conductive film on a chip-mounting surface of the substrate, and patterning the conductive film into a plurality of patterned wirings and a plurality of lands which cover the entire openings of the first through holes and partially constitute the patterned wirings and into a conductive pattern which covers the entire openings of the second through holes; (c) mounting two or more semiconductor chips on the chip-mounting surface of the substrate; (d) mounting external connection terminals at the first through holes from a terminal-mounting surface opposite to the chip-mounting surface and connecting the semiconductor chips to the external terminals through the lands; (e) encapsulating the plural semiconductor chips in one-piece with a resin for encapsulation; and (f) dividing the resulting substrate for the individual semiconductor chips by cutting the substrate and the resin from the terminal-mounting surface of the substrate in this order by defining a cutting position using the second through holes and the conductive pattern.
Still further, the present invention provides with a resin-encapsulated semiconductor device comprising; a substrate for mounting a semiconductor chip including thereon a patterned wiring, a plurality of first through holes for external connection and a plurality of lands which cover the entire openings of the first through holes and partially constitute the patterned wiring, a plurality of semiconductor chips being mounted on the substrate, the semiconductor chips being encapsulated with a resin, and terminals for external connection being mounted on a surface opposite to a chip-mounting surface of the substrate and electrically connected to the semiconductor chips via the lands, wherein the plurality of semiconductor chips are divided into two or more groups and each of the groups is encapsulated in one-piece with a resin.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.